Q3 2026 Aehr Test Systems Earnings Call
Greetings and welcome to the Air Test systems fiscal 2026% third quarter financial results Conference call. At this time all participants are in a listen only mode. A question and answer session will follow the formal presentation. If anyone should require operator assistance during the conference. Please press.
Star Zero on your telephone keypad. Please note. This conference is being recorded I will now turn the conference over to your host Jim Byers of Pinedale Wilkinson Investor Relations you may begin.
Thank you operator, good afternoon, and welcome to Air Test systems third quarter fiscal 2026 financial results Conference call.
With me on today's call are Air Test Systems', President and Chief Executive Officer gain Ericsson and Chief Financial Officer, Chris you.
Before I turn the call over to gain and Chris I'd like to cover a few quick items.
And even right after market closed air test issued a press release announcing its third quarter fiscal 2026 results.
That release is available on the company's website at <unk> Dot com.
This call is being broadcast live over the Internet for all interested parties and the webcast will be archived on the Investor Relations page of the company's website.
And I'd like to remind everyone that on today's call management will be making forward looking statements that are based on current information and estimates and are subject to a number of risks and uncertainties that could cause actual results to differ materially from those in the forward looking statements.
These factors are discussed in the company's most recent periodic and current reports filed with the SEC. These forward looking statements, including guidance provided during today's call early valid as of this date and are test systems undertakes no obligation to update the forward looking statements.
And now with that I'd like to turn the conference call over to gain Erickson President and CEO.
Thanks, Tim Good afternoon, everyone and welcome to our third quarter fiscal 'twenty six earnings conference call I will start with an update on the key markets driving our business and strong demand, we're seeing particularly from AI and data Center infrastructure. Chris will then review our financial results and we'll open up the call for questions.
Very pleased with the strong momentum in our business across multiple market segments highlighted by more than $37 million in quarterly bookings and a book to bill ratio exceeding three five X.
Our effective backlog, which includes the backlog of $38 7 million at the end of the fiscal third quarter plus additional bookings received since the end of the quarter is now over $50 million, a new company record after generating approximately $20 million in bookings in our first in our fiscal first half.
We're already two and a half times that in second half bookings and now expect to come in on the high side of the $60 million to $80 million in second half bookings I mentioned last quarter.
Demand continues to accelerate across both packaged level in wafer level burn in driving driven by increasing semiconductor complexity power requirements and deployment and mission critical AI networking automotive and industrial applications.
As devices become more advanced the need for comprehensive test and burn in is becoming essential to ensure reliability and performance. This is driving growing adoption of our solutions across multiple markets.
So let me start with wafer level burn in.
During the quarter, we continued to make progress in growing our installed base and expanding to new customers with our wafer level burn in solutions.
Our wafer level burn in is really hot right now I guess pun intended we received a $14 million follow on production order from our lead wafer level AI accelerator processor customer for multiple new fully automated Fox XP wafer level burn in systems to be used in data center training and inference applications.
The order included multiple additional Fox XP wafer level test and burn in systems, each configured to test nine 300 millimeter wafers in parallel along with a set of era's proprietary Fox wafer pack full wafer contactor is any fully integrated Fox wafer pack Ottawa liner with each system to enable hands free operation and high.
Volume production.
In addition, the order included multiple additional Fox wafer pack Ottawa liners to upgrade the customer's existing installed base of Fox XP systems to full automation.
It was the first company to successfully demonstrate and ship a wafer level burn in solution for AI processors.
Our Fox XP systems configured for very high power high current AI processors began shipping last year and provides the highest power per wafer capability available in the market delivering up to thousands of amperes of current per wafer.
This order further expands our installed base of Fox XP systems, and Thats full automation across the production lines highlighting the growing importance of wafer level burn in to ensure the long term reliability of today's very high power high current AI processors.
We're also actively engaged with multiple additional AI processor companies on benchmark evaluations and expect to make meaningful progress with those opportunities.
Our benchmark evaluation program with a top tier AI processor supplier continues to make good progress, but it's taken longer than we originally expected. This was due to a technical misunderstanding on the clock configurations, which created some challenges with the initial wafer pack designs.
While we wish we had been able to catch this earlier, we're taking device data now on their wafers with the current wafer pack design and redesigning the wafer packs to meet the new requirements. We expect to continue to provide them with additional data on this wafer pack design as well as the improved one over the next several months.
We have several other companies ranging from suppliers of data center focused AI accelerator processors to edge AI processors, and Cpus, they are providing us with information on their devices and roadmaps and asking about our wafer level burn in capabilities and recommendations for Brennan of their next generation devices.
There is significant interest in doing wafer level burn in for devices that are expected to put an inning advanced packages such as Tsmc's cost base packages that include other dies, such as HBM DRAM stacks other compute AI processors, and photonic or electrical based transceiver chipset.
Waiting out bad devices before they're packed together with these other devices is significantly cheaper than the yield loss. If these are burned in at package level and the entire multi chip packages thrown away.
Okay.
For burn in Silicon Photonics devices, we recently announced a major new customer win a major new silicon photonics customer with an initial order for multiple high power Fox XP wafer level burn in systems for devices aimed at the Hyperscale data center optical interconnect market.
This customer is developing advanced silicon photonics based transceivers for data center networking and optical Io applications to address the rapidly accelerating demand for high speed fiber optic communication links and Hyperscale AI and cloud data centers. These.
These multiple systems or for both ensuring qualification in high volume production and include a Fox XP wafer level burn in system configured to test nine wafers in parallel a fully integrated wafer pack auto aligner multiple Fox NP wafer level burn in systems and multiple full set of Fox wafer pack for wafer contactor is for production engineering.
And new product introduction.
These systems are all scheduled to ship in this fiscal fourth quarter, ending may 29 to 26 <unk>.
<unk> also provided a forecast for multiple additional XP production systems over the next year as they ramp capacity support next generation Hyperscale data center deployments.
We believe this win positions are to participate in what could be a significant multi year expansion of silicon photonics production driven by the growth of fiber optic interconnects and Hyperscale AI data centers.
Additionally, we received a follow on order from our lead Silicon photonics customer for both the new high power Fox XP wafer level system, and an upgrade of an existing system to our latest high powered fully automated configuration.
We now have fully integrated our systems and our liners with their autonomous guided robots that carry around the 300 millimeter FOUP. So the customer can operate in a fully lights out hands free operation.
They too have given us a forecast for additional production systems as they ramp into next calendar year.
As data center architecture scale to support AI cloud computing and high performance networking fibre optic interconnects offer significant advantages over copper wiring included in higher data rates lower power consumption longer reach improved thermal performance and reduced electromagnetic interference. These advantages are driving rapid adopt.
<unk>, a silicon photonics transceivers across Hyperscale and enterprise data centers worldwide and increasing demand for cost effective production proven burn in solutions that can ensure device quality and long term reliability at volume.
<unk> is the market leader in wafer level burn in for Silicon Photonics, Transceivers with a large installed base at leading global semiconductor in photonics companies. The companies are our Fox XP platform enables high parallelism high temperature and high power wafer level burn in allowing customers to stabilize their devices a critical mass.
Any factoring process step in the laser diode emitters for these devices as well as to identify early life failures before packaging to net ticket we reduced the cost of test.
And gallium nitride and silicon carbide power semiconductors, we've been working with our lead Gan production customer on a significant number of new devices aimed at multiple markets that include automotive intermediate bus conversion datacenter and electrical infrastructure. This continues to be a great partnership.
And we continue to work on and believe we have solved the key challenges with full wafer burn in again devices on silicon.
Wafer level burn in of their Gan devices for both qualification production burn in is an extremely valuable capability that is critical to their roadmap and plan and we're both very excited to see then meets our growth projections.
We continue to see Gan on Silicon carbide power semiconductors is critical to the electrification of the world's infrastructure. In addition to key market opportunities such as data center power delivery electric vehicles and charging infrastructure.
We won a new customer in silicon carbide this quarter with a company in Taiwan focused on the Asian, and particularly greater EV market.
Greater China EV market, sorry, they placed an order for a small configured Fox XP system for qualification and production key elements of their decision included our ability to demonstrate all the capabilities they needed with our systems in Fremont, California, as well as the feedback they received from customers with data and conquer.
And erez wafer level burn in systems used for testing and burning silicon carbide wafers across a large number of silicon carbide suppliers.
We see an uptick in activity and forecast from the Silicon carbide players. This makes sense as we see major OEM EV suppliers in Japan, and Germany rollout a number of new Evs later this year.
ZB suppliers understand the value and need for wafer level burn in of the six devices before they are put into modules containing many devices in parallel for the EV engine driving burgers. This is well understood in the industry and air is seen as the market leader and proven solution for wafer level burn in silicon and silicon.
Silicon carbide devices used in EV inverters by a significant number of EV suppliers.
We're still converts conservative about forecast from customers and while we have plenty of capacity and believe we have the world's most cost effective and highest performance wafer level burn in solution on the market, we're not yet counting on significant revenue from this segment to return yet however, it could still be a very good performing segment.
For Us next year.
We'll see.
Now, let me talk about wafer level burn in for memory.
Our engagement with a key memory supplier continues to progress with additional wafer testing just this last week, we've been able to achieve the correlation. They are asking for are now in discussions about test system specifications needed for their next generation flash memories and in particular their high bandwidth flash devices.
We hope to close on this in the next few months, which would lead to a development agreement to supply systems and wafer packs to them. After a 12 to 18 month development of our new memory optimized blades for our Fox XP NP multi wafer test and burn in platform.
But we're also now in discussions with other key memory suppliers that also produce high bandwidth memory, the new DRAM standard being used in AI Gpus. In addition to standard DRAM and flash memories.
HBM memories as I referred to are embedded into multi chip packages with advanced substrates, such as the co ops packaging from TSMC.
And videos roadmap as aggressively pushing towards higher capacity faster HBM standards to address the memory wall in AI training and inference.
Coming road map transitions from <unk> to four in 2026, and then from HBM for <unk> five in the following years with capacity per GPU expected to increase from 80 gigabytes in the 100 class to over a terabyte and the Rubin ultra by 2027 for semi analysis.
We are seeing the added potential for <unk> insertion with our Fox multi wafer test and burn in system roadmap that extends to flash high bandwidth flash DRAM and HBM memories.
This is a key focus for air this year to drive to an agreement to work with these customers in the development of the enhancements needed to extend our Fox systems to these markets. This is a market that we believe could drive orders in fiscal 'twenty seven with ramps in fiscal 'twenty eight.
Now turning to package level burn in let me start by highlighting that we're trying to change our own vocabulary from packaged part burn in to package level burn in this may seem subtle but to give a little background. Traditionally there was one semiconductor integrated circuit per single package. The package was used to protect the die from elements and wire out to a standard pattern of pins or <unk>.
That allowed easy handling assembly onto a printed circuit board.
This pattern or pitch between pins is much much larger than the pitch on the individual die. So contacting the devices is very different for us between our packaged level and wafer level solutions. Historically about 20 years ago. There was a package concept called multi chip packages, where multiple individual die where wire bonded into a single.
Package. This was driven at the time for size and performance typically this was much more expensive and generally this faded out in time two other smaller package sizes.
Recently in the last handful of years they have been three major drivers of the need for new multi chip packages, but this has been called advanced packaging or modules rather than mcps, one driver, which is the biggest one is that the multi decade long trend that was referred to as Moore's law has come to an end. This law was the number of transistors was.
<unk> every one five to two years, while the die size was staying the same and therefore costs were staying flat or decreasing.
This allowed higher and higher performance smaller die and therefore lower cost die to be made via process improvements or die shrinks. This drove the industry for 40 years or so until around 2010, plus or minus when shrink started to slow materially.
Dennis several applications such as AI processors extremely high density memory, such as flash and DRAM power semiconductors.
Being driven by massive markets, such as data center, AI and electric vehicles, the extremely high value a need for multiple devices in the same package came to fruition.
At this time it was functionality and feasibility that drove this we now referred to these devices in two camps really <unk> wafer level die level and packaged level, where packaged level includes both single die per package and also multi chip modules or advanced package multi die packages such as those found in AIG.
<unk>.
With HBM DRAM stacks multi stack flash Ssds and also multi die silicon carbide modules for EV, inverters and charging infrastructure.
At least I hope this helps as we talk through this and make it more clear what the differences between wafer level and packaged level. You may catch me still same package part at times adult habits are hard to break, but we'll try to refer to these as package level from now on.
Okay. During the quarter, we announced a key production win with our lead packaged level Hyperscale customer. This customer is a premier large scale data center provider and selected are for production burn in of their next generation significantly higher power AI processor with an initial production order of our high power Sonoma systems.
This next generation AI ASIC is expected to move to production later this year and is believed to be even higher volumes than the first debate device that this customer is ramping our Sonoma systems on right now.
We also expect a significant near term follow on order from this customer for package level burn in systems to support their high volume manufacturing other custom AI processors today. The current one used in data center training and inference.
They are forecasting a substantial expansion of Sonoma systems purchases beginning in the second half of calendar 2026, and continuing into 2007.
We believe it's likely that there is overlapping ramps between the current and next generation devices, which should significantly expand both our installed installed base and long term consumable opportunity with this customer.
We're also engaged with multiple potential customers for packaged level qualification test of AI accelerators, Asics network processors and edge AI processors for automotive and robotics. These engagements also represent opportunities to move to production burn in overtime and interestingly about half of these have also expressed interest in wafer.
The level burn in in addition to our package level burn in solutions.
Yesterday.
Afternoon. In fact, we received an order from a brand new customer for Sonoma to be used for reliability qualification of their new AI processor.
But they may also do production burn in with this device, which they can do with the exact same platform using Sonoma.
This momentum reinforces our leadership in high power burn in for AI processors, the broader demand environment remains very strong industry forecast index indicate that Hyperscale data center capacity are expected to nearly triple by 2030, driven by new both new builds and upgrades to existing infrastructure. This is driving substantial growth.
In high performance semiconductors, and in turn demand for advanced burn in solutions as we've noted before as our installed base of systems continues to grow our consumables, which includes our wafer pack full wafer contact us for wafer level and our burn in board and modules for package level burn in can continue to grow beyond our systems.
While this year has been lighter in terms of consumable sales particular wafer packs, we believe it's an outlier.
Some customers had bought systems ahead of that have the need and have grown into capacity and this seems to be running its course, we believe over time, our controls business will consistently be at 30% or more of our total revenue and our margins will increase the sales of these value add consumables growth.
To support growing demand, we're continuing to scale manufacturing capacity. In addition to our Fremont expansion. This quarter, we will begin shipping Sonoma systems from one of our current contract manufacturers, adding.
Capacity of more than 20, additional Sonoma systems per month.
This meaningful increase at this meaningfully increases our ability to support future growth with expanding AI infrastructure deployments and our recent manufacturing capacity enhancements. We believe we're well positioned to support significant growth both in our wafer level package level burn in systems as customers ramp production.
With strong second half bookings, so far and a strong funnel of additional orders expected. This quarter. We believe we are well positioned to exit the fiscal year, ending may 29, with a strong backlog and deliver significant revenue growth in fiscal 2007.
We currently expect full year fiscal 2006 revenue to be on the high side of the $45 million to $50 million range provided last quarter.
We also expect our bookings for the second half of the fiscal year to be on the high side of the $60 million to $80 million range provided last quarter.
More broadly we believe we have a clear path to sustained long term growth as our installed base expands across AI silicon photonics power semiconductors memories and other high performance applications.
Our semiconductor performance and reliability requirements continue to rise Vernon is becoming increasingly critical across a growing set of applications. We believe <unk> is uniquely positioned as the only provider operating both wafer level and package level burn in solutions at scale and with that I'll turn it over to Chris. Thank you again and good afternoon.
Everyone.
I'll begin with bookings in backlog, then walk through our third quarter financial performance cash position outlook and investment activity.
The company recognized bookings of $37 2 million in the third quarter of fiscal 2026 significantly higher than the $6 2 million in the second quarter. As we have received multiple purchase orders for Fox systems wafer packs and Sarah Ottawa liners from different customers, what AI silicon photonics silicon carbide applications.
At the end of the quarter.
Our backlog was $38 7 million during the first five weeks of the fourth quarter, we received an additional $12 2 million in bookings.
This increase was driven primarily by a major new silicon photonics customer for wafer level burn in with an initial order for multiple Fox systems for both engineering qualification and high volume production, which we recently announced.
With this recent bookings or effective backlog, which includes our quarter end backlog plus additional bookings received since the end of the third quarter has now grown to a record of $50 9 million, providing strong visibility for the remainder of fiscal 2026 and positioning us for significant growth for fiscal 'twenty.
Seven.
Our strong bookings include increased demand for both wafer level and package part package level burn in solutions.
We believe this reflects the proven value of this differentiated solutions, which are increasingly integral to the production and reliability to strategies of our customers in the AI data center and other key markets we serve.
Turning to our Q3 performance.
While we do not provide quarterly guidance, our third quarter revenue of $10 3 million was in line with our internal expectations due to delayed orders.
Q3 revenue was slightly below consensus and down 44% from $18 3 million in prior year period.
The decline was primarily driven by lower shipments of Fox systems and wafer packs.
Wafer level burn in business.
Partially offset by stronger demand flow Sonoma systems from a hyperscale customer.
Contact to revenues, which include wafer packs for wafer level burn in business in <unk> and bps full package level burn in business totaled 3 million, representing 29% of total revenue in the third quarter.
This compares to $5 9 million or 32% of revenue in Q3 last year.
non-GAAP gross margin for the third quarter was 36, 5% compared to 42, 7% a year ago.
The year over year decline reflects lower overall sales volume and a less favorable product mix as last year quarter include a higher proportion of higher margin wafer pack revenue.
non-GAAP operating expenses in the third quarter was $6 3 million flat from $6 3 million in Q3 last year.
We continued to invest significant resources in our AI benchmark and memory projects.
During the quarter, we recorded an income tax benefit of $8 million, resulting in an effective tax rate of 19, 9%.
non-GAAP net loss for the third quarter, which excludes the impact of stock based compensation and acquisition related adjustments was $1 5 million or a loss of <unk> <unk> per diluted share.
Compared to net income of 2 million or <unk> <unk> per diluted share in the third quarter of fiscal 2025.
non-GAAP net loss for the third quarter exceeded consensus by <unk> <unk>.
Turning to cash flow, we used $3 7 million in operating cash during the third quarter.
We ended the quarter with $37 1 million in cash cash equivalents and restricted cash.
Some 31 million at the end of Q2.
The increase was primarily due to proceeds from our at the market or ATM equity program.
During the third quarter of fiscal 2020, we raised $10 5 million in gross proceeds through the sale of about 269000 shares.
Since the end of Q3, we raised $19 5 million.
Proceeds through the sale of about 477000 shares.
And with the $9 9 million, we raised in Q2, we have now fully utilized a $40 million available under the ATM and have sold over one 3 million shares at an average price of $35 in 30 days.
We also announced this afternoon that will be changing our fiscal year end from the last Friday on May two to last Friday of June effective after our fiscal year ends.
On May 29 2026.
Our new fiscal year 2027 will begin on June 27, 2026 and end on June 25th 2027.
Continuing with the 445 calendar.
As a result, we will have one month of financial results for May 30th 2026 to June 26, 2026, which will be reported as a transition period when we.
File our quarterly Form 10-Q in the first quarter ending September 25 2026, we.
We believe our new fiscal year will align more closely with our reporting periods, although customers and appears in the semiconductor test equipment industry.
Moving to our outlook for the full year fiscal 2026, ending on May 29, 2026. We currently expect total revenue to be on the high side of the $45 million to $50 million range provided last quarter and non-GAAP net loss per diluted share to be between.
Negative 13, and negative <unk> <unk> for the full fiscal year.
We expect our gross margin to improve as our manufacturing activity increases to support higher sales volume and better absorb our fixed costs.
We also expect to return to profitability on a non-GAAP basis in the fourth quarter fiscal 2026.
Lastly, looking at the Investor Relations calendar.
Tests will be participating in two investor conferences over the next couple of months.
We'll be meeting with investors at the Craig Hallum Institutional Investor Conference, taking place in Minneapolis on May 28, and we will be presenting and meeting with investors on June 2nd at the William Blair 46th annual growth conference taking place in Chicago.
Hope to see some of you had this conferences.
That concludes our prepared remarks, we're now happy to take your questions. Operator. Please go ahead.
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Do you have a question or comment.
Our first question comes from Mark shooter with William Blair. Please proceed.
Hey, Jim Hey, Chris you have March year on year for Jed door genre.
Hey, Mark Hey, Mark.
Congrats on all the progress, especially with the Hyperscale or.
I'm just curious how you guys are looking at this internally.
What percentage of Gpus, or ASIC or XP use do you think are burnt in today.
How do you guys size the vector space.
That's a really good question and I think we're still getting our arms around a little bit here.
I would say that.
We've been a little bit surprised at how.
There are many devices are not yet doing production burn in.
One of the things that we mentioned it strategically when we purchased in cow what.
18 months ago, or so Intel does type of burden than they were.
<unk> called qualification reliability, Bernann, which all processors go through fact, all semiconductors, it's what determines there.
<unk> time reliability specs and that they will last long enough et cetera, so sort of a onetime deal you do with a large number of devices to do the statistics on it.
Then certain devices go through a screening in production to weed out at for modalities because of the failure rate is higher than the market will bear.
So in <unk> doing this with a large number of AI customers, but actually prior to that wasn't doing any production burn in when we acquired them. We've now because of the capacity we have in terms of people and infrastructure, we have been able to capture this large hyper scaler and are engaged with multiple others.
One of the things that I've been surprised at is that how many of the I guess, particularly the ASX suppliers don't.
Don't do production burn in yet or are talking about doing it.
That goes for a lot of different devices that are out there from edge robotic.
A sick network processors and even <unk>.
And what we should be careful of GPU, because everybody just associated GPO only with.
With Nvidia, but not all devices are burnt and still today and so there are certain ones that are there are certain ones that arent and.
And even within our company. They may have some of their products are burnt Dan and others are however, the common theme is they are all moving to burn at.
The data is out now that there are solutions out there like Sonoma or of the wafer level burn in of our Fox systems that can cost effectively do it and so now there is a very viable alternative to doing it at the system level or the rack level. We've said in the past that many of these guys would actually build it all the way to the rack and then at the cyst.
Some integrator they would burn it in for a week or two and weed out the infant mortality to ship it or in some cases with ASIC suppliers. They just shifted into their data centers and dealt with the fallout.
So it's.
It's growing.
Trying to think if I try and put a percent I think on asics it might be.
Bye.
Unit quite like SKU, I mean, I don't know if its 20%.
Maybe it's 5% of the number so most asics are not printing.
I would say on the AI accelerators that are out there across a wide variety.
Maybe half, but then what's happening there is the processors are gaining higher power from generation to generation and breaking all the tools that are out there. So even the tools that were out there and I'm not giving any inside information whatsoever, but just cut.
Classically understood like Nvidia as processors of three couple of generations ago compared to their current ones Terrapower is substantially more which would require new tools and the ones that they're working on and others in a year and out and again, just what's publicly available break to the current tools.
And so there's a continuous roadmap and so even within our Sonoma platform, we're continuing to add capabilities to one of the key features we have is the ability to adapt it and at higher and higher current and power as you go forward. So.
There is.
How many times you hear as CEO say you are at the early innings, but this is still at the kind of the beginning phases of this and over time people will be buying a lot more burn in systems.
As a percentage you meaning to cover the percentage of total and then just didn't share quantity.
I appreciate all the color Dana that's very helpful.
To zero in a bit on your hyperscale or customer can you bring us into the role a bit here and.
What was the decision process to go with packaged level right now packaged part of your remarks patented level versus wafer level and do you see a transition potentially with this customer to move to wafer level and if you get a new customer.
Is there do you think that yes.
At the same decision or is there a track towards wafer level.
Should credit can you help us out with that okay. So to be fair.
Three years ago. If you would've asked me, we said that I've said this before can you do wafer level burn in of AI processors, I think we would have said absolutely not.
We didn't have the power in the system and the belief was that there werent that test modes that we now understand there are to be able to do it and now as we've gone from customer to customer across a wide variety. There is commonality is about at that allow us to be able to confidently tell them. We can do wafer level burn in so.
Prior to that it was whether you did package level burn in or nothing or not or did it at I'd say the rack level. Okay. So.
So people first step as I do I do burn in and they're going to default to thinking I'm going to do it at the package level, but then what we're seeing and I mentioned this before we have customers.
I don't want to get too carried away here, but.
The last two customers that were in the last two weeks.
<unk> is our ISR package level burn in BP and Vernon really runs kind of the wafer level side of things the customer will come in and say I want to talk about packaged level at about halfway through the tour. There like what is that we talk about wafer level or like how do I do that and so we kind of joke about it around here at <unk>, but the reality.
<unk> is we don't care, which side you go to we are both specifically on the hyper scaler and I've said this out loud before.
The first device they run with us it's not their first device, but it's the first one they went to production on is on Sonoma. Their second device. They just awarded US with production for that water and are planning the ramp of that with US right now that are already on our roadmap talking about the third device and they've asked us about.
The DFT to specifically put into the third device group because they would like to consider that for wafer level on our Fox systems.
I think that sort of a progression that we will see and I would actually imagine large customers that have multiple different product lines. Some they would do wafer level on and suddenly they might do package level on.
It becomes particularly valuable when you have a like a package that has multiple.
Processors in it.
And all the HBM memory.
Hi.
So in those particular ones I mean, the coop substrate is more expensive.
Then the silicon itself with the processor, which sounds crazy. So there would be very interested in doing the wafer level to screen out the die before they have to throw away everything else. So I think there is a progression over time where people well.
Move towards wafer level on the things that Ken.
Default to packaged level, where they can't.
That's really helpful. Thank you again.
Thanks Mark.
The next question comes from Christian Schwab with Craig Hallum. Please proceed.
Hey, Chris.
Hey, good afternoon. Thanks.
Thanks for a tremendous amount of detail regarding.
The different target markets and and your success in each one of them.
The most common question I receive is.
Is there a way to.
Gauge.
Over a multiyear timeframe, obviously you gave guide.
Guidance for <unk>.
For this year.
In support of substantial growth.
Following year with.
Bookings in hand, and others to come.
But it has been if you had enough time to give some thought to.
The range of potential outcomes over a multiyear timeframe.
That you guys could do and in combination.
<unk> of your target markets and potential entry into the market every market down the road.
So.
The short answer is we have.
The long answer is.
It's.
We're just really cautious about trying to get too carried away with our projections, but the numbers are.
Very significant.
If you just because particularly now that theres some hs the high bandwidth memory.
Kind of angle wellness thing too if you look at the dollar spend that people are going to do.
Whether you call it compute or AI or if you look at that.
The compute capability right that are going into training and inference in data centers inference in edge automotive robotics.
Sure.
That number of different applications in the way people are using it and deploying it.
The amount of silicon wafers is staggering.
And why people would talk about these enormous dollars.
Those devices are.
Process or has always been Burton.
It feels like I'm, contradicting what I said earlier.
Widely known that Intel and AMD. The primary processor suppliers of the world burnt in every one of their processors and always have.
When the first Gpus were coming out those were using graphics. They were not burn 10, and the initial people that are all related to AI or our foundries and they're out looking for burning capability. There were no burn in systems in the foundry <unk> models, and so people werent spending out there.
Enormous amounts of money on test and it's growing and they're going to be spending a significant portion of their test budget on burn and going forward I hear things I mean, I hear constantly from the customers rotating through so the the terms are.
Multi hundreds of millions of dollars for.
Our package level burn in wafer level burn in <unk>, if you say it displaces package level is even higher.
The average actual price per unit time of wafer level is actually more expensive than packaged level, but the yield.
Pays for all of it.
And so it's cheaper to the customer to spend more money.
And so the Tam is our larger there if you look at the memory side of things if you look at the memory spend.
The number of Fabs that are coming out in the next.
Five years, what percentage of budget is for their test budget. If these are big numbers and so the spend is.
In burn in is probably total spend measured in.
Multiple billions of dollars per year.
In the next couple of years.
On an annual basis and the question is will then wait a minute how come you guys arent.
$500 million and the answer is we think that we have a very good opportunity to significantly grow our packaged level in wafer level business across the biggest segments that are driving burden and one of the reasons, we're leading with putting infrastructure and capacity in place to be able to have the conversations we're having with these customers.
There are throwing out some really big numbers.
And at.
And a warm may youre getting carried away here, but.
It's an awesome place to be and it's not only silicon carbide for Evs.
Lots of people are wondering if the evs are ever going to make it as you guys know the history.
People got ahead of themselves and I was even saying that its a commodity you guys not no. One is going to be we're not all going to be driving evs, but the terms. In these segments are are significantly larger than anything we ever talked about.
Power semiconductor side.
Great that gives me enough to work with no other questions. Thanks again.
Thanks Christian.
The next question comes from Max <unk> with Lake Street Capital markets. Please proceed Max.
Hey, guys. Thanks for taking my questions.
First wanted to start out here, we look at the demand environment from the package level and wafer level.
They both demand seems strong on both sides of the business here, but I mean.
To me it looks like wafer level system is all PC on the demand side and maybe the order side can you let me know if I'm.
Wrong, there, but anything else you can add as well.
The challenge with our business and for all of our shareholders as we we know how to be lumpy.
And.
By having more markets and more customers it can make it less lumpy, but the ASP of a production order set in.
In wafer level burn in can be $10 million to $20 million in in order, let's say okay.
Packaged level can be that big or bigger too okay. So when they come in it looks like Oh right now we see demand on both.
Significant now the engagement and the.
Work to get our wafer level burn in is definitely harder than packaged level.
The obvious reason is in many cases, we're already testing the part for the call on our tool.
So now they have to just say Oh, I need to buy a whole bunch of them and add automation and go to production does it make sense on wafer level. What we've found is that there is a learning process.
Both sides, a little bit but to understand.
How they can use our tool to be able to test their part.
In some cases, they're like Okay. I know if I just did this it would make it a lot easier, but it's too late I already taped out this park that would be an example, theres benchmark I mean right now.
It's like they are having to use some a little fancier wafer pack to do it and if they just did some specific DFT. They could use a very simple wafer pack. The same wafer pack, we're using for like silicon photonics or silicon carbide in some of these others their vocabulary with US is I'll I'll be able to do that but the nextgen, but can you just work around it with the.
Current one well, it's kind of harder the other one as I mentioned I wanted to get a little too carried away I mean, I get pretty techie on these things, but we had a miscommunication on the clocks, which.
Something really simple candidly, but if you do them wrong. It doesn't work and so we've had the jury rig some stuff to actually get it to work and we're going to spend it to make it work nobody is freaking out about it because this isn't rocket science, but it would be that it will be something we would never mess up again with that customer because that we now both have the same vocabulary.
One is always easier.
So theres a little bit more startup thing with the wafer level burn in but if you are technically astute and engaged and you look at it youre not going Oh. This isn't going to work you. Just go okay cash that's too bad debt pay down let's keep going.
So there is a learning process, we're getting faster at it and.
I think over time wafer level burn in.
The silicon carbide Silicon Photonics customer we won this last quarter. It was just yes. I mean, there was there was no on wafer benchmark. It went from can you do it to how fast can you deliver.
Okay.
Think that is a natural progression youll see it in our packaged level and youll see it in our wafer level over time, where customers will engage don't know we can do it and that just six months ago.
Alright.
Perfect. Thank you that's it for me thank you.
Thanks Max.
Thank you once again at.
Once again, if you have a question or comment. Please press star one. The next question comes from Larry <unk> with <unk> capital. Please proceed.
Yes.
Again your contract manufacturer that Youre, starting up what is that.
Sure.
And when would be fully capable of doing your 'twenty sooner.
<unk>.
There.
Sure.
They've already built.
During the process of building the first batch I would say, especially way of looking at it.
There is it's a little more complicated than the way I described but theres sort of multi there is actually two contract manufacturers together and then one feeds into the other one the first one the one the feeds and the other one did their prototypes they sent to US we were going through a kind of a.
And acceptance process to validated to work out any kinks.
Then those go to the other contract manufacturer for final system integration and shipping.
One is we when we were out there we visited them last September I think.
Did kind of an audit of the facility power infrastructure and cleanliness and they did a kind of a remodel similar to ours. If people have seen it it's all whitened fancy clean floors.
More clean room space. So that we can actually build these things in a clean room area. They had facilities that we are doing some stuff for solar as it turns out.
So we were able to leverage from that and.
That is in place now and we think first products will be ready to ship to customers this quarter through may.
And what we want to make sure as they're ready to go by late summer when.
When we see the Sonoma ramp hitting.
Alright.
The room. My question are you keeping any capacity or are you planning on producing those systems in Fremont as well or is Oh, yes for sure. But this is in addition to we've kind of talked about like about a 20 system per month capacity here from an infrastructure and footprint perspective, wed actually still need to hire smart people maybe pick on a shift.
But we will use we use that facility for like large volume orders of the same SKU. If you will make it simple and then we'll use we'll continue to make Sonoma systems here and all of the Xps will be built out of here all of Fox products.
And then.
Did I hear you say that your first expected XP sales to H B M and H beam customer will be <unk>.
This calendar year or this next fiscal year 'twenty, yes.
Yes, I didn't quite say anything I was a little more elusive than that on purpose. What I will tell you is that we have identified some interesting opportunities with the HBM probably that new <unk>.
It has.
Some interesting challenges that people would really like to do this wafer level burn in on and between our Fox system has it stands and the roadmap that we've been working on as people, though with.
With the team of people here Corey memory extension to the Fox system to add what we would call channel modules into the box that make it memory focused.
We think that Theres some real overlap there that just as you know Larry you followed this law that's an uptick.
Yes.
And.
And it is it is in parallel with flash now.
I would say that it would be.
Yes.
A little bit of an uptick.
And in order to actually had good uptick I'll agree with you, but right now I am excited about the discussions.
So the flash engagement.
Do you think that will bear fruit on the enterprise side here shortly before hbf gets underway.
We have heard that youre going to.
It's a good question.
I think it really is up to the customer.
Kind of the timing of what we would build would be something that would be a super set that could do both.
So yes, if hbf were delayed a little bit maybe we would intercept their standard product they've asked us to build it the definition discussion has been to do both.
In some ways hbf is easier okay.
Because if you start saying, it's all flash in a lot of times, what happens is people say well I want to be able to test everything I've ever had before and as the as the interfaces evolve they tend to converge and voltages and speed or whatever and if you say well I want legacy it's like Wow.
Okay I've got to support this all voltage or something on a device you don't make anymore. So part of the challenge for US is to try and kind of converge on what do you really need going forward. What are you going to spend the money they probably never buy a system for legacy products from us in general.
So I think thats one of the challenges we got to work through.
Well, that's all I have.
You got a lot of iras require.
It is it is it is.
Find new guys I'm, telling you.
<unk>.
Yeah.
Vernon and Alberto and R&D teams and.
Nick.
Our wafer pack team is very busy right now.
And we're doing some things to offload that adding additional resources, we're hiring anybody.
Looking for a great job with a company that's growing.
It is now we've got a lot of reqs out there and we're looking for great people.
So it's.
It sounds like Arizona, Florida.
Congratulations I know you've been working on it for a good while we get to this point.
Thanks, Larry.
Thank you.
Thank you.
Once again, if you have a question or comment please indicate so by pressing star one on your phone.
Yeah.
Alright, operator, whether if there is no other question as well and on that really happy note.
And.
As always if you guys have any questions. Please feel free to reach out to us if you happen to be in the Bay area.
I don't want to try and stop five we're always happy to.
Give us a short towards two key investors and things like that and we look forward to a great quarter talking to you next quarter I guess with our new fiscal year now.
Our quarterly earnings will be the same time, the next time and then there'll be.
Guess of one month push value or something like that but should work out this will be a good thing for our customers, which honestly that's the key to all of this alright.
Alright, Thank you very much folks bye bye.
Okay.
Thank you. This concludes today's conference and you may disconnect. Your lines at this time. Thank you for your participation.
