Is Intel Keeping a (Wonderful) Secret From the Market Regarding Its 18A Node?

Intel appears to be positioned to deploy ASML high-NA (HNA) EUV lithography earlier than previously disclosed, potentially on its 18A node which is ramping now, rather than waiting for 14A in 2028. The company has publicly disclosed at least three HNA machines (including acceptance testing of an EXE:5200 unit), reported processing ~30,000 wafers/quarter on HNA tools, and may have secured additional machines (industry reports suggest 5–6 for 2024); HNA tools cost roughly $400 million each but promise higher density, fewer process steps and yield advantages versus low-NA multi-patterning. Intel claims yield parity between low-NA and high-NA on 18A/14A test flows and will showcase its first 18A-produced chip (Panther Lake) soon, creating a material competitive event that could alter TSMC/Intel dynamics if confirmed.

Analysis

Market structure: If Intel actually deploys high-NA (HNA) in 18A during the 2025–26 ramp, near-term winners are INTC (manufacturing differentiation) and ASML (HNA pricing and backlog); suppliers of EUV resists/pellicles (small-cap specialty chem) also benefit. Losers: TSM (TSM) faces a potential share and margin pressure at the bleeding edge if it waits, while smaller pure-play foundries lose optionality. Expect leading-edge cost-per-good-die to fall where HNA replaces multi-patterning, shifting gross-margin advantage toward first movers over a 2–4 year window.

Risk assessment: Tail risks include HNA underperformance (yield shortfalls >10% vs low-NA expectations), ASML delivery/export curbs to China, or Intel capex/dilution if fabs underutilize machines; any such event can compress INTC equity by >30% in a stress scenario. Immediate catalysts: CES (next week) and Intel’s Panther Lake launch; short-term (3–6 months) watch wafer/yield disclosures; long-term (2–5 years) is customer share gains/losses. Hidden dependencies: limited HNA tool count (single-digit annual units), specialised resists/pellicles, and customer acceptance cycle times.

Trade implications: Tactical play is asymmetric: small, time-boxed long exposure to INTC and ASML and a calibrated relative short vs TSM to express manufacturing-moat rotation. Use option structures to cap downside (calendar or vertical spreads) around key catalysts (CES, FQ releases). Reweight into capital-equipment and specialty chemical suppliers, reduce exposure to commoditized foundries if Intel proves HNA parity.

Contrarian angles: Consensus assumes full HNA substitution; reality may be hybrid (HNA on 20–40% of EUV layers), muting cost impacts and elongating TSM’s catch-up. Market may be underpricing ASML’s pricing power but overpricing INTC’s near-term commercial upside. Historical parallel: EUV adoption was multi-year despite technical breakthroughs; regulatory/geopolitical shocks could flip winners quickly.

Key Decisions for Investors

• Establish a tactical 2% long position in INTC ahead of CES (enter within 1 week); implement via a directional call spread: buy Jan 19 2027 35C / sell Jan 19 2027 50C sized to 2% portfolio notional; set stop-loss if spread loses 15% or if Intel discloses wafer-yield miss >5% vs guidance.
• Allocate 1.5% long to ASML (ASML) for 12–24 months via equity or Jan 2028 LEAPS (buy Jan 19 2028 650C) to capture HNA backlog; trim on any quarter where ASML order backlog growth <5% sequentially or semiconductor capex softness emerges.
• Implement a pair trade: long INTC 2% / short TSM 1.5% (dollar-neutral) to express potential foundry share shift; exit or hedge within 6–12 months if TSM announces HNA adoption timeline acceleration or if INTC fails to confirm HNA usage by Panther Lake launch.
• Use options as protection: buy one-quarter TSM Jan 2027 60P (or nearest strike) sized to cover downside of the short if geopolitical export controls are announced; maintain this hedge until ASML order book updates or 2026 Q2 results clarify tool deployment.