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Sony’s next-gen handheld rumoured to outperform Xbox Series S

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Sony's next-gen handheld (Project Canis) is reportedly targeting a high-end portable spec: 24 GB LPDDR5X on a 192-bit bus, a 16-CU RDNA 5 GPU, a 6-core Zen 6 CPU configuration (four Zen 6c efficiency + two Zen 6 performance) on TSMC 3nm within a 15–30W power envelope. Leaks claim rasterization slightly outperforms Xbox Series S and ray/path tracing is "massively ahead," while Valve is said to target a 2028 Steam Deck 2 launch—delayed by global DRAM/NAND shortages—and may use an off-the-shelf Zen 6/RDNA 5 APU. Sony and AMD are also reportedly developing FSR 5 / PSSR 3 AI upscalers to compete with Nvidia's DLSS, suggesting intensified competition in handheld GPU and AI-upscaling capabilities.

Analysis

A move upmarket in handheld hardware is less a product play than a re-pricing of the mobile gaming value chain: higher ASP devices shift profit pools toward IP licensors and foundries while elevating per-unit component bills (memory, power management, RF). That means near-term margin volatility for OEMs but structurally higher gross dollars for suppliers that can secure allocation, creating a two-tier supplier market where scale and foundry partnerships matter more than chip architecture alone. Supply-side constraints will be the gating factor for commercial success. Limited bleeding-edge wafer and premium DRAM allocation will favor large customers with volume commitments, compressing the addressable launch window for smaller entrants and forcing either longer ramp timelines or higher pre-order prices; expect production cadence and yield announcements to drive meaningful stock moves in 3–9 month bursts. On the software side, upscaling/AI pipelines — not raw raster or RT numbers — will determine perceived parity with incumbent GPU vendors. If alternative upscalers gain developer traction within 12–24 months, Nvidia’s differentiated software moat in gaming diminishes, shifting investor focus back to data-center exposure as the primary value driver for NVDA. Key catalysts and tail risks: shipment cadence, wafer yields and DRAM pricing will be the earliest hard data points; delays or yield shortfalls are binary downside events while faster-than-expected software adoption could compress competition quickly. Positioning should therefore be staged around foundry/memory updates and early market share telemetry rather than launch headlines alone.