Hyperscalers plan roughly $700 billion in AI data‑center spending this year, underpinning broad demand across chipmakers. Nvidia reported 73% YoY revenue growth in its latest quarter as GPUs remain the backbone of AI training; AMD is gaining inference and CPU share, Broadcom sees custom AI ASICs contributing >$100M in fiscal 2027, Micron expects HBM demand to grow ~40% annually, and TSMC holds dominant foundry and packaging positions. These dynamics point to sustained revenue and margin tailwinds for leading semiconductor suppliers tied to AI infrastructure buildout.
TSMC’s packaging and advanced-node scale are the linchpin of the current AI stack, but the real second-order rents will flow to narrow suppliers: high-end substrate/assembly houses, interposer makers, and the EUV tool chain. Expect margin capture to bifurcate — TSMC and a handful of packaging specialists can sustainably expand gross margins, while commodity logic fabs and non-specialist OSATs will see margin pressure as customers pay up for guaranteed CoWoS-like capacity. HBM tightness is not just a DRAM pricing story; it’s a wafer-capacity and substrate-allocation problem with a 6–18 month lag between capex decisions and supply response. That lag creates a window where one- to two-quarter demand shocks (model retrains, open-source LLM momentum pauses) can swing spot HBM prices and company-level revenue by double digits, then mean-revert as backfills and additional NAND/DRAM lines come online. On the competitive front, hyperscalers’ in-house ASIC moves and potential vertical integration into packaging/foundry tools are the largest structural tail risks over a 2–5 year horizon. If a few hyperscalers internalize key packaging steps or secure exclusive multi-year foundry capacity, it would cap upside for incumbents; conversely, any regulatory push against dominant software ecosystems could accelerate multi-vendor optimization and benefit second-tier GPU/CPU/ASIC designers faster than consensus expects.
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