
Researchers have successfully demonstrated a scalable control solution for silicon spin qubits, utilizing a heterogeneously integrated cryo-CMOS 'chiplet-style' architecture operating at milli-kelvin temperatures. This innovation directly addresses the critical interconnect bottleneck and mitigates heat and crosstalk issues inherent in scaling quantum systems. The study found only minimal qubit performance degradation, primarily attributed to manageable parasitic heating rather than electrical noise, validating the viability of this approach for developing utility-scale quantum computers.
This research presents a significant advancement in quantum computing by demonstrating a viable solution to the critical interconnect bottleneck that has hindered the scaling of spin qubit systems. By successfully controlling silicon-based qubits with a heterogeneously integrated cryo-CMOS chip operating at milli-kelvin temperatures, the study validates a 'chiplet-style' architecture. The key finding is that the control system, which contains approximately 100,000 transistors, has a minimal impact on qubit performance. A slight degradation in single-qubit fidelity (0.07%) and a modest reduction in two-qubit coherence time (around 20% at high clock frequencies) were observed, but these effects are attributed primarily to manageable parasitic heating rather than prohibitive electrical noise. This distinction is crucial, as thermal management is a more tractable engineering challenge, particularly within the demonstrated heterogeneous framework that allows for separate cooling pathways. The low power consumption of the control cells, approximately 20 nW MHz⁻¹ per 100 mV pulse, is well within the capacity of commercial dilution refrigerators, reinforcing the architecture's scalability. The work, supported by Microsoft (MSFT) and utilizing equipment from Keysight (KEYS), represents a tangible de-risking of a major engineering hurdle for silicon-based quantum computers.
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