Intel cancels part of its next-gen Diamond Rapids Xeon lineup, report claims — Xeon 7 will drop models with 8 memory DIMMs to focus only on 16-channel CPUs for extra memory throughput

Intel has removed the 8-channel Diamond Rapids variant from its roadmap and will ship Diamond Rapids Xeon 7 exclusively as 16-channel processors, a move the company says will simplify the platform (ServeTheHome). The 16-channel design, paired with 2nd-generation MRDIMMs and higher DDR5 speeds (up to ~12,800 MT/s), is expected to roughly double memory bandwidth to about 1.6 TB/s versus ~844 GB/s, uses the new LGA9324 socket and tops out at 192 cores across four 48-core tiles (SMT/hyper‑threading deferred to Coral Rapids). While the change boosts high-end memory throughput and server performance, it eliminates lower-cost 8CH SKUs—potentially ceding volume and multi‑socket flexibility—and may leave Intel vulnerable on core‑count parity as AMD readies up to 256‑core EPYC parts next year.

Analysis

Intel confirmed removal of the 8‑channel Diamond Rapids (8CH) variant from its Xeon 7 roadmap, stating it will simplify the platform and focus exclusively on 16‑channel processors. The cancelled 8CH would have succeeded existing 8CH Xeon 6 6700P/6500P SKUs, which means Intel is foregoing a lower‑cost segment and intermediate socket options that historically drove volume.

The 16‑channel pivot materially increases memory throughput: 16 DDR5 channels plus 2nd‑generation MRDIMMs lift peak speeds from ~8,800 MT/s to ~12,800 MT/s and boost memory bandwidth to about 1.6 TB/s from ~844 GB/s. Xeon 7 will adopt the LGA9324 socket and top at 192 cores across four 48‑core tiles, while simultaneous multithreading is deferred to the subsequent Coral Rapids family.

This strategic narrowing enhances high‑memory throughput appeal for performance‑sensitive workloads but risks ceding price‑sensitive and multi‑socket market share to AMD, which is rumored to ship up to 256‑core EPYC Venice on 2nm Zen 6. Sentiment metrics show a mildly negative tone toward the move and a modest market‑impact score (0.35); near‑term outcomes will hinge on OEM adoption, pricing strategy, MRDIMM supply and AMD's Venice launch timing.

Key Decisions for Investors

• Reassess exposure to Intel‑dependent server suppliers and consider hedging or modestly reducing positions that rely on lower‑cost 8‑channel Xeon SKUs, since Intel's cancellation may cede volume and multi‑socket advantages
• Consider selectively increasing exposure to AMD or its ecosystem partners ahead of EPYC Venice if core‑count leadership and OEM design wins translate into share gains, while monitoring AMD launch timing
• Monitor three near‑term indicators before larger allocation changes: Intel pricing and roadmap updates for Diamond/Coral Rapids, MRDIMM and DDR5 (12,800 MT/s) supply ramps, and OEM/data‑center customer adoption or multi‑socket support announcements
• For longer‑horizon allocations, favor data‑center operators and workloads where higher memory bandwidth (~1.6 TB/s) materially improves performance and TCO, but validate cost impact versus throughput benefits before increasing exposure