AMD Zen 6 Medusa Point CPU Spotted With 10 Cores And More L3 Cache

An engineering sample labeled AMD Plum-MDS1 (100-000001713-31_N) surfaced in Geekbench showing 10 cores / 20 threads, a 2.4GHz nominal base clock but ~2.0GHz observed in the test, and 10MB L2 + 32MB L3 (42MB total) cache — L3 is ~33.3% larger than recent Strix/Gorgon Point APUs. Being an early Zen 6 Medusa Point APU engineering sample, performance is inconclusive, but the larger L3 and new architecture suggest potential mobile APU uplift if validated; AMD-targeted timing in leaked roadmaps is 2027.

Analysis

A leak of a next-generation AMD mobile APU should be treated as a signal rather than a finished product; the market impact will be determined by share gains in OEM design cycles, pricing power on system ASPs, and the cadence of software optimization. If OEMs re-rate the competitive set and accelerate refreshes, expect a reallocation of ~5–10% of the low-to-mid laptop segment’s discrete GPU unit demand into APUs over an 12–24 month window, a channel shift that would compress unit volumes for entry discrete GPU SKUs and shift incremental OEM margin toward SoC vendors.

On the supply side, any meaningful architectural step-up at advanced nodes will tighten foundry and advanced packaging demand, increasing bargaining leverage for TSMC/ASML and creating a multi-quarter lead-time effect on wafer starts and substrates. That can raise cost of goods sold for ODMs and push OEMs to accept higher ASPs or smaller BOM margins; conversely, it creates a tangible capex tailwind for foundries and lithography suppliers in the 12–36 month horizon.

Competitively, incumbents that rely on discrete GPUs (NVDA) for low-end graphics and integrated players (INTC) for mobile will face different pressures: discreet GPU unit demand is most at risk while Intel’s mobile roadmap must accelerate or concede share. Software-level tuning (drivers, ISV optimizations) is a gating factor — real-world UX gains often lag silicon announcements by 9–24 months, muting short-term financial impact.

Primary downside scenarios are execution-related: delays, poor yields, thermal limits, or lack of OEM design wins can erase the upside; upside catalysts include announced design wins from top-3 OEMs, foundry guidance upgrades, and visible share movement in panel-level shipments. For investors, the signal is constructive but operationally contingent — favor instruments that capture multi-year secular benefit while limiting near-term execution risk.

Key Decisions for Investors

• Long AMD (AMD): buy 24–36 month LEAP call position sized 2–4% of equity book to capture multi-year upside from mobile design wins; hedge with a 10–20% notional protective put to limit downside to execution risk. R/R: asymmetric — limited to premium/put cost vs 2–4x upside if share gains materialize.
• Pair trade — long AMD / short Intel (AMD long / INTC short): equal notional 12–24 month pair to express mobile CPU share rotation; size conservative (net delta near zero) because Intel execution can re-price quickly. R/R: captures relative share transfer; risk is Intel reclaiming competitiveness via process or pricing moves.
• Express foundry tailwind via TSMC (TSM): buy a 12–24 month call spread on TSM to monetize higher advanced-node wafer starts and packaging demand while capping premium outlay. R/R: limited downside to premium paid, moderate upside if AMD-led ramps increase wafer demand mid-single-digit percent.
• Tactical hedge on discrete GPU exposure — small short NVDA (NVDA): trade a 12–18 month put spread sized 0.5–1% notional to reflect potential erosion in low-end discrete GPU volume. R/R: limited downside and capped payout; keeps exposure small due to NVDA’s dominant secular AI exposure.