Teradyne, Inc. (TER) Presents at Goldman Sachs Communacopia + Technology Conference 2026 Transcript

Teradyne said semiconductor test represents roughly 80% of revenue, while robotics and product test each account for about 10%. CEO Greg Smith highlighted that all major businesses are exposed to the AI build-out, spanning wafer and package testing through product and system-level testing for data-center infrastructure. He noted semiconductor test has recently grown quickly, modestly increasing its revenue mix.

Analysis

The relevant valuation question is whether AI-related tester demand is becoming a multi-quarter content story rather than another semiconductor-test utilization cycle. TER has the strongest leverage to complex compute, networking and custom-ASIC test insertion, where rising pin counts, power requirements and system-level validation can lift test time and ASPs even if unit growth moderates. The less obvious read-through is that higher test intensity can constrain customers' production ramps: tester lead times and installed-base utilization become a bottleneck, giving TER pricing power but also making quarterly revenue recognition more dependent on customer capex timing.

Near-term, the conference remarks are not independently actionable absent backlog, order-growth, gross-margin or customer-capex disclosures; the likely market reaction should be limited. Over the next 1-3 months, hyperscaler custom-silicon commentary, NVIDIA/AMD supply-chain data, and foundry advanced-node utilization are the useful confirmation points. Over 6-18 months, a broader mix of custom accelerators is structurally favorable because each new device family requires incremental characterization and production test, but this same diversification reduces the chance that any single platform creates a sustained tester shortage.

The key competitive risk is that AI's fastest-growing test spend may accrue disproportionately to memory and high-bandwidth-memory test, where Advantest has stronger exposure, rather than to TER's compute-oriented installed base. A second-order loser from persistent tester tightness is lower-volume analog/consumer customers, which may face reduced access to engineering resources and delay program ramps; that would reinforce TER's mix shift but increase cyclicality if AI capex pauses. The thesis is falsified by a sequential decline in semiconductor-test orders, evidence of shortening tester lead times, or customer inventory correction before new AI programs move from engineering qualification into high-volume production.

Key Decisions for Investors

• Maintain TER as a watch-list long rather than chase conference-driven strength; initiate only after the next earnings release confirms sequential semiconductor-test order growth and stable-to-higher gross-margin guidance. Target a 6-12 month position sized for a high-beta semiconductor-capex cycle; exit on a material backlog/order-guide reset.
• Express the compute-test versus memory-test split through a 3-6 month relative-value basket: long TER / short Advantest (6857 JP) only if disclosed AI compute and networking orders accelerate while HBM-related memory-test indicators soften. The trade is invalidated if HBM supply constraints or memory-capex revisions remain the dominant incremental test-spend driver.
• Use SOXX or SMH weakness following a broad macro-driven semiconductor selloff to build TER exposure, rather than treating the conference as a catalyst. The favorable setup requires AI infrastructure demand to remain intact while TER's multiple compresses with the group; avoid if the selloff is accompanied by foundry-utilization or hyperscaler-capex cuts.
• Monitor robotics separately from the AI tester thesis: do not underwrite a higher TER multiple until robotics bookings show improving industrial demand. Continued weakness there can offset semiconductor-test operating leverage and limit consolidated margin upside even if AI tester revenue grows.